Principal DDR Verification & Silicon Bring-Up Engineer

SiMa.ai, Inc.; San Jose (CA); On-site; USD 204,000 - 316,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

SiMa.ai, Inc. in San Jose, CA is seeking a Principal Engineer to lead DDR verification and silicon bring-up efforts.

The role focuses on functional verification of DDR controllers and DDR-phy across block, sub-system, and SoC levels, plus bring-up on silicon and emulation debugging. You will define test benches with UVM/SystemVerilog, develop initialization sequences for silicon bring-up, and collaborate with MLSoC Architecture and Hardware/Software teams to advance DDR performance and

Qualifications

• 15+ years of experience in functional verification and silicon bring-up
• Very good experience with UVM and SystemVerilog based verification
• Working experience on DDR or LPDDR4/5 protocols
• DDR bring-up and debug on Silicon
• Experience and skill set for silicon bringup/debug in the lab
• Good debug and problem solving skills

Responsibilities

• Participate in DDR architecture, micro-architecture and feature discussions and reviews
• Define and develop DDR test bench components using UVM & System Verilog
• Bring up and testing of DDR at MLSoC level in full-chip test environment
• Develop and execute a test plan
• Verification execution of DDR functionality and performance measurements
• Manage debug of test and regression failures
• Work closely with the Architecture, MLSoC Hardware and Software teams
• Generate required DDR initialization sequence for Silicon bring up and debug in the lab
• Participating with MLSoC SW team for DDR silicon bring up and debug

Skills

UVM

SystemVerilog

DDR protocols

Debugging

Silicon bring-up

Education

BS/MS in EE or CS

Tools

Emulation

Job description

SiMa.ai, Inc. in San Jose, CA is seeking a Principal Engineer to lead DDR verification and silicon bring-up efforts.

The role focuses on functional verification of DDR controllers and DDR-phy across block, sub-system, and SoC levels, plus bring-up on silicon and emulation debugging. You will define test benches with UVM/SystemVerilog, develop initialization sequences for silicon bring-up, and collaborate with MLSoC Architecture and Hardware/Software teams to advance DDR performance and