Senior DDR5/DDR6 SystemVerilog Verification Engineer

Montage Technology, Inc; Johns Creek (GA); On-site; USD 120,000 - 150,000; Full time

Job summary

You will partner with validation and test teams to ensure coverage aligns with post-silicon needs and contribute to a robust verification flow across product generations.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering or equivalent.
• 5+ years of relevant work experience.
• Good understanding of CMOS circuit design.
• Strong understanding and hands on experience in building UVM Testbenches from scratch.
• Proficient with digital and analog simulation tools such as VCS, Xcelium, Verdi.
• Excellent debugging and problem solving skills.
• Strong understanding of DDR5 protocol or CXL 2.0 spec.

Responsibilities

• Take ownership of system-level verification for DDR5 and early DDR6 DIMM subsystems and PMIC IP.
• Build, maintain, and improve UVM SystemVerilog testbenches and verification infrastructure.
• Create directed and constrained-random stimulus, functional coverage, assertions, and automation.
• Review architecture and specs with a verification mindset to identify ambiguities and gaps.
• Collaborate with validation and test teams to align pre-silicon coverage with post-silicon needs.
• Reproduce issues in simulation to aid root cause analysis during silicon bring-up.
• Explore AI-assisted verification tools where they add value.
• Keep regressions healthy and push fixes that stick.
• Mentor junior engineers and share verification knowledge.

Skills

UVM testbenches

DC/AC verification

debugging skills

DDR5 protocol knowledge

Education

BS or MS in Electrical/Computer Engineering

Tools

VCS

Xcelium

Verdi

Job description

You will partner with validation and test teams to ensure coverage aligns with post-silicon needs and contribute to a robust verification flow across product generations.