Principal Verification Engineer

OSI Engineering; United States; Hybrid; USD 170,000 - 196,000; Full time

Job summary

A leading chip and silicon IP provider is looking for a Principal Verification Engineer to work in a hybrid role. This position involves leading verification efforts, implementing testbenches, and ensuring quality. Ideal candidates will have significant experience in System Verilog and UVM methodology with a strong educational background in Electrical Engineering. Join a team that values collaboration and innovation while working on advanced technologies in attractive locations such as San Jose, CA, and Morrisville, NC.

Qualifications

• 10+ years of verification experience with MS in Electrical Engineering.
• 7+ years of verification experience with PhD in Electrical Engineering.
• Experience with verification of DDR memory interfaces is desirable.

Responsibilities

• Lead full-chip and block-level verification efforts.
• Define and implement verification plans and testbenches.
• Support silicon bring-up, lab testing, and debugging.

Skills

System Verilog

UVM methodology

Linux/Unix scripting

Complex technical solutions

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Cadence IMC

Jenkins

Job description

Overview

A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, you’ll work alongside world-class engineers to develop advanced technologies that make data faster and more secure.

Responsibilities

• Technical leader for full-chip and block-level verification
• Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers
• Implement testbenches, monitors, and scoreboards using UVM methodology
• Achieve functional and code coverage goals to ensure quality and completeness
• Support silicon bring-up, lab testing, and debug in partnership with the System team
• Contribute to the development of verification flows, tools, and methodology
• Mentor and guide junior engineers within the team

Requirements

• Proficient in System Verilog or Verilog with significant UVM methodology experience
• Significant Experience with standard ASIC Verification flow/software tools
• Simulation tools: Synopsys VCS, Cadence Xcelium
• Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
• Experience with scripting in Linux/Unix environments
• Verification of DDR memory interfaces is desirable
• Experience working in Analog/Mixed-Signal Products is desirable
• Verification Methodologies: SVA (System/Verilog Assertions) is desirable
• Regression Management: Jenkins (CI/CD Integration) is desirable
• Demonstrated ability to lead and drive complex technical solutions
• A strong commitment & ability to work in cross functional and globally dispersed teams
• MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience

Location

San Jose, CA; Agoura Hills, CA; Morrisville, NC; Johns Creek, GA (Hybrid)

Employment type

Full-time

Salary

Base pay range: $170,000.00/yr - $196,000.00/yr (DOE)

No 3rd party agencies or C2C