Principal PCIe Verification Engineer — On-Site San Jose

SiMa Technologies, Inc.; San Jose (CA); Hybrid; USD 220,000 - 296,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

SiMa Technologies, Inc. in San Jose, CA is seeking a Principal Engineer, PCIe Verification to lead functional verification of PCIe controllers and PHYs across block, sub-system, and MLSoC levels.

The role involves bring-up, debugging on emulator, and UCIe interface work on next generation projects. You will define PCIe test benches with UVM/SystemVerilog, run tests in block and full-chip environments, develop test plans, and drive code coverage and assertions.

Qualifications

• 12+ years in functional verification and silicon bring-up/debug.
• Strong UVM and SystemVerilog verification experience.
• PCIe Gen4/5 protocols and silicon bring-up on silicon a plus.

Responsibilities

• Define and develop PCIe test benches using UVM and SystemVerilog.
• Bring up and test PCIe in block and full-chip environments.
• Develop and execute a PCIe test plan and verify EP/RC functionality.
• Lead code coverage reviews and functional coverage closure.
• Collaborate with Architecture and MLSoC hardware/software teams.
• Debug PCIe issues in emulation and real silicon bring-up.

Skills

UVM & SystemVerilog

PCIe Gen4/5 experience

C/C++/Python

Debugging & problem solving

Team collaboration

Education

BS/MS in EE or CS

Job description

SiMa Technologies, Inc. in San Jose, CA is seeking a Principal Engineer, PCIe Verification to lead functional verification of PCIe controllers and PHYs across block, sub-system, and MLSoC levels.

The role involves bring-up, debugging on emulator, and UCIe interface work on next generation projects. You will define PCIe test benches with UVM/SystemVerilog, run tests in block and full-chip environments, develop test plans, and drive code coverage and assertions.