Principal Verification Architect (DDR6 & SystemVerilog/UVM)

SmartRecruiters, Inc.; San Jose (CA); On-site; USD 198,000 - 248,000; Full time

Job summary

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffers.

The role drives verification strategy and execution for complex digital designs, collaborating with RTL and design teams to ensure functionality, performance and product requirements are met. Deep SystemVerilog and UVM expertise are essential, with DDR memory experience a plus.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM, including development and optimization of UVM-based verification environments.
• Experience defining verification strategies and developing verification plans from design and product specifications.
• Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff.
• Work closely with RTL and design engineers to ensure designs meet functional and performance requirements and are effectively verifiable.
• Analyze specifications, design implementation, and verification results to identify functional gaps and design issues.
• Drive debugging and resolution of complex verification failures.
• Develop scalable and reusable verification components, methodologies, and best practices.
• Identify and lead improvements in verification efficiency, quality, performance, and reuse.
• Participate in architecture, feasibility, design, and technical reviews.
• Provide technical guidance and mentorship to verification engineers.
• Serve as a technical expert for assigned verification methodologies and tools.
• Communicate verification progress, coverage, technical risks, and readiness to engineering leadership and project stakeholders.

Skills

SystemVerilog

UVM

Technical leadership

Mentoring

Debugging

Collaboration

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or CS

Job description

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffers.

The role drives verification strategy and execution for complex digital designs, collaborating with RTL and design teams to ensure functionality, performance and product requirements are met. Deep SystemVerilog and UVM expertise are essential, with DDR memory experience a plus.