Senior ASIC Verification Engineer - DDR Memory IP

Synopsys Inc; Sunnyvale (CA); Presencial; USD 150.000 - 230.000; Tempo integral

Resumo da vaga

Synopsys Inc. is seeking an experienced verification engineer to lead DDR PHY and memory subsystem IP verification. You will translate architectures into executable tests, build scalable UVM testbenches, write assertions, and drive coverage to catch protocol violations before tape-out.

You will mentor junior engineers, collaborate with design teams, and integrate AI-assisted verification tools into our workflow, enabling faster, more robust silicon validation across product families.

Qualificações

• Bachelor’s degree in electrical or computer engineering with 8+ years of hands-on ASIC verification experience.
• Deep proficiency in UVM methodology and SystemVerilog; built test benches that found bugs.
• Understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows.
• Knowledge of DFI protocol, memory controllers, or memory subsystem integration.
• Strong scripting in Perl or Python for automation, result parsing, and flow development.
• Proven debugging skills across RTL and gate-level simulations.
• Experience with AI-assisted verification tools is a plus.

Responsabilidades

• Define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specs into executable verification strategies.
• Design and write constrained-random SystemVerilog testbenches using UVM, building reusable verification components that scale across product families.
• Write SystemVerilog assertions and functional coverage models to close coverage gaps and catch protocol violations.
• Debug RTL and gate-level simulation failures, working with design engineers to root-cause issues in complex memory interface logic.
• Perform code coverage analysis and drive coverage closure, identifying untested paths and corner cases that matter.
• Mentor verification engineers earlier in their careers, reviewing test benches, debugging strategies, and verification plans.
• Integrate AI-assisted verification tools and workflows into the team's methodology.

Conhecimentos

UVM

SystemVerilog

ASIC verification

Debugging RTL

Test benches

Formação

Bachelor's degree in Electrical/Computer Engineering

Ferramentas

Perl

Python

DFI protocol

Descrição da vaga

Synopsys Inc. is seeking an experienced verification engineer to lead DDR PHY and memory subsystem IP verification. You will translate architectures into executable tests, build scalable UVM testbenches, write assertions, and drive coverage to catch protocol violations before tape-out.

You will mentor junior engineers, collaborate with design teams, and integrate AI-assisted verification tools into our workflow, enabling faster, more robust silicon validation across product families.