Lead Silicon Verification Architect (DDR5/NoC/HBM)

AMD; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

AMD is seeking a Senior Staff Silicon Design Verification Engineer in San Jose to drive verification strategy for high‑speed memory controllers (DDR5, LPDDR6, HBM4), Crypto and NoC IPs, at IP and SoC levels. You will architect, develop, and utilize simulation/formal environments and lead verification teams toward first‑pass silicon success.

The ideal candidate has a strong track record in pre‑silicon verification, excellent communication and leadership skills, and hands‑on experience with UVM,

Qualifications

• Hands-on verification of high-speed memory controllers (DDR/LPDDR/HBM).
• Experience leading verification teams of 5+ engineers.
• Development of UVM and SystemVerilog testbenches; use of simulation tools.

Responsibilities

• Lead verification of high-speed Crypto and NoC designs with DDR5/LPDDR6/HBM4.
• Architect and develop IP- and SoC-level verification environments.
• Lead and manage verification teams, plans, tracking, and delivery to programs.
• Create comprehensive verification plans, testbenches, and test cases.
• Collaborate with design, architecture, and software teams on verification strategies.
• Apply advanced verification methodologies and assertion-based verification.
• Mentor junior engineers and foster a collaborative team environment.

Skills

UVM

SystemVerilog

Formal verification

Leadership

Education

BS with 8+ yrs experience

Tools

Synopsys VCS

Cadence Xcelium

Questa Formal

Job description

AMD is seeking a Senior Staff Silicon Design Verification Engineer in San Jose to drive verification strategy for high‑speed memory controllers (DDR5, LPDDR6, HBM4), Crypto and NoC IPs, at IP and SoC levels. You will architect, develop, and utilize simulation/formal environments and lead verification teams toward first‑pass silicon success.

The ideal candidate has a strong track record in pre‑silicon verification, excellent communication and leadership skills, and hands‑on experience with UVM,