Senior ASIC Verification Architect – UVM, DDR Memory

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC verification engineer to define and drive verification plans for DDR PHY/memory IP, and to build reusable UVM-based testbenches across product families. You will author SystemVerilog assertions, coverages, and debug complex RTL issues in collaboration with design teams.

The role emphasizes mentoring, spearheading coverage closure, and integrating AI-assisted verification workflows to improve prediction of silicon behavior before tape-out.

Qualifications

• Bachelor’s degree in electrical or computer engineering with 8+ years of ASIC verification experience.
• Deep proficiency in UVM methodology and SystemVerilog with proven test-benches.
• Strong understanding of DDR memory architecture, DDR PHY design, timing, training and calibration.

Responsibilities

• Define and track verification test plans for DDR PHY and memory IP blocks.
• Design and write constrained-random SystemVerilog testbenches using UVM.
• Write SystemVerilog assertions and functional coverage models to close gaps.
• Debug RTL and gate-level simulation failures with design engineers.
• Perform code coverage analysis and drive coverage closure.
• Mentor verification engineers and review test benches and plans.
• Integrate AI-assisted verification tools and workflows into the team's methods.

Skills

UVM verification

SystemVerilog

DDR memory/IP verification

DFI protocol knowledge

Perl or Python scripting

RTL/gate-level debugging

AI-assisted verification tools

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

UVM

SystemVerilog

Python

Perl

Job description

Synopsys, Inc. is seeking an experienced ASIC verification engineer to define and drive verification plans for DDR PHY/memory IP, and to build reusable UVM-based testbenches across product families. You will author SystemVerilog assertions, coverages, and debug complex RTL issues in collaboration with design teams.

The role emphasizes mentoring, spearheading coverage closure, and integrating AI-assisted verification workflows to improve prediction of silicon behavior before tape-out.