Principal DDR6 Verification Architect

Renesas Electronics Corporation; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas Electronics Corporation is seeking a Principal Design Verification Engineer to lead verification for next-generation semiconductor memory interface products, including data buffer silicon. The candidate will drive verification strategy and ensure functionality and performance, with deep SystemVerilog and UVM expertise.

Preferred background includes DDR/ memory interfaces; ownership of verification efforts and ability to mentor a team are essential.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering, Computer Engineering, CS, or related field.
• Extensive semiconductor design verification experience with ownership of complex verification.
• Expert-level SystemVerilog proficiency and strong UVM experience.

Responsibilities

• Lead verification strategy and execution for complex designs at block and system level.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and environments.
• Provide technical guidance and mentorship to verification engineers and communicate progress to leadership.

Skills

SystemVerilog

UVM

Mentoring

Verification strategy

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Testbenches

Verification environments

Job description

Renesas Electronics Corporation is seeking a Principal Design Verification Engineer to lead verification for next-generation semiconductor memory interface products, including data buffer silicon. The candidate will drive verification strategy and ensure functionality and performance, with deep SystemVerilog and UVM expertise.

Preferred background includes DDR/ memory interfaces; ownership of verification efforts and ability to mentor a team are essential.