Principal ASIC Physical Design Lead – Fullchip

Cisco Systems, Inc; San Jose (CA); On-site; USD 251,000 - 363,000; Full time

Job summary

Cisco Systems, Inc. is seeking a senior ASIC designer to own the fullchip floorplanning process in a fast-growing hardware team.

You will collaborate across RTL, DFT, EDA vendors, and physical design to optimize performance, power, and die size while leveraging AI-augmented tool flows. The role emphasizes deep experience with floorplanning, clock meshes, and signoff methodologies within a multi-foundry environment, with a strong focus on cutting-edge process technologies and post-silicon

Qualifications

• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Proficient with major EDA tools used in advanced ASIC flows.

Responsibilities

• Fullchip Floorplan by understanding the architecture, foundry guidelines, and IP placement constraints.
• Collaborate with system and package design teams to incorporate requirements into fullchip floorplan.
• Perform hierarchical implementation flow including partition, pin assignment, clock plan, and bump planning.

Skills

Floorplanning

RTL2GDSII flow

Clock planning

Power integrity

Python AI tools

Education

Bachelor’s degree in Engineering

Master’s degree in Engineering

PhD in Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc. is seeking a senior ASIC designer to own the fullchip floorplanning process in a fast-growing hardware team.

You will collaborate across RTL, DFT, EDA vendors, and physical design to optimize performance, power, and die size while leveraging AI-augmented tool flows. The role emphasizes deep experience with floorplanning, clock meshes, and signoff methodologies within a multi-foundry environment, with a strong focus on cutting-edge process technologies and post-silicon