Pre-Silicon Digital Verification Engineer UVM & Formal

Hardware FYI; Sunnyvale (CA); On-site; USD 130,000 - 200,000; Full time

Job summary

Apple is seeking a pre-silicon digital verification engineer to join its mixed-signal ASIC team in Sunnyvale, CA. You will verify complex digital IPs, create verification plans, and own testbench development using SystemVerilog Assertions and UVM-based simulation.

You will also explore formal verification and other advanced techniques to ensure bug-free designs on first tapeout. As part of a small, high-performing group, you will review code, collaborate with architects and designers, and

Qualifications

• Experience in verification of digital IPs for ASICs.
• Ability to build verification plans and testbenches.
• Familiarity with SystemVerilog Assertions and constrained random testing.

Responsibilities

• Verify complex digital IPs within mixed-signal ASIC projects.
• Own creation of verification testbenches and test cases.
• Develop verification plans to exercise functional and stress scenarios.
• Participate in code reviews to improve verification quality.
• Explore formal verification and alternative verification techniques.

Skills

SystemVerilog

UVM

Formal verification

Digital ASIC verification

Testbench development

Tools

SystemVerilog tooling

Formal verification tools

UVM environment

Job description

Apple is seeking a pre-silicon digital verification engineer to join its mixed-signal ASIC team in Sunnyvale, CA. You will verify complex digital IPs, create verification plans, and own testbench development using SystemVerilog Assertions and UVM-based simulation.

You will also explore formal verification and other advanced techniques to ensure bug-free designs on first tapeout. As part of a small, high-performing group, you will review code, collaborate with architects and designers, and