Pre-Silicon Digital Verification Engineer: SystemVerilog/UVM

Apple Inc.; Sunnyvale (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Sunnyvale seeks a pre-silicon digital verification engineer to verify complex digital IPs for mixed-signal ICs.

You will work with system architects and digital designers to translate specifications into verification plans and block-level tests, and own the verification testbench creation, using formal verification and UVM-based simulation. You will participate in code reviews of other blocks, learn advanced techniques such as formal verification and mixed-signal simulation, and

Qualifications

• BS and a minimum of 3 years of relevant industry experience

Responsibilities

• Collaborate in developing precise design specifications for digital control blocks
• Use design specifications to create block and chip level verification plans.
• Architect and create block level verification elements
• Assist in architecting chip and system level verification environments.
• Use System Verilog and UVM to develop drivers, tests, reference models and checkers
• Debug test failures and work with designers to develop fixes
• Use functional and code coverage to track progress and gauge tapeout readiness.

Skills

Digital verification

Constrained random verification

Clock domain crossing verification

Object oriented programming

Verification planning

Education

BS in Electrical Engineering or related field

Tools

SystemVerilog

UVM

Formal verification

Job description

Apple Inc. in Sunnyvale seeks a pre-silicon digital verification engineer to verify complex digital IPs for mixed-signal ICs.

You will work with system architects and digital designers to translate specifications into verification plans and block-level tests, and own the verification testbench creation, using formal verification and UVM-based simulation. You will participate in code reviews of other blocks, learn advanced techniques such as formal verification and mixed-signal simulation, and