Digital Verification Engineer - First Silicon

Apple Inc.; San Francisco (CA); Sur place; USD 129 300 - 225 300; Plein temps

Résumé du poste

Apple is seeking a digital‑focused DV engineer to enable first silicon for IP designs in the San Francisco Bay Area. You will drive pre‑silicon verification, establish DV methodology, develop test plans and environments, and sign‑off for RTL tape‑out.

The role emphasizes SystemVerilog/UVM and scalable DV infrastructure for IP/SoC verification. Responsibilities include creating test plans, stress testing with SystemVerilog/UVM, debugging regressions, and using modern verification tools.

Qualifications

• Minimum requirement of a bachelor's degree.
• Preferred BS degree in a technical subject with 3+ years of relevant industry experience or equivalent.

Responsabilités

• Study design specification and create test plans.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Connaissances

SystemVerilog

UVM

Test benches

C/C++

Python

Perl

TCL

PCIe

USB

DDR

Formal verification

UPF

Waveform viewers

Automation scripting

Formation

Bachelor's degree

Description du poste

Apple is seeking a digital‑focused DV engineer to enable first silicon for IP designs in the San Francisco Bay Area. You will drive pre‑silicon verification, establish DV methodology, develop test plans and environments, and sign‑off for RTL tape‑out.

The role emphasizes SystemVerilog/UVM and scalable DV infrastructure for IP/SoC verification. Responsibilities include creating test plans, stress testing with SystemVerilog/UVM, debugging regressions, and using modern verification tools.