Pre-Silicon Digital Verification Engineer

Hardware FYI; Sunnyvale (CA); On-site; USD 130,000 - 200,000; Full time

Job summary

Apple is seeking a pre-silicon digital verification engineer to join its mixed-signal ASIC team in Sunnyvale, CA. You will verify complex digital IPs, create verification plans, and own testbench development using SystemVerilog Assertions and UVM-based simulation.

You will also explore formal verification and other advanced techniques to ensure bug-free designs on first tapeout. As part of a small, high-performing group, you will review code, collaborate with architects and designers, and

Qualifications

• Experience in verification of digital IPs for ASICs.
• Ability to build verification plans and testbenches.
• Familiarity with SystemVerilog Assertions and constrained random testing.

Responsibilities

• Verify complex digital IPs within mixed-signal ASIC projects.
• Own creation of verification testbenches and test cases.
• Develop verification plans to exercise functional and stress scenarios.
• Participate in code reviews to improve verification quality.
• Explore formal verification and alternative verification techniques.

Skills

SystemVerilog

UVM

Formal verification

Digital ASIC verification

Testbench development

Tools

SystemVerilog tooling

Formal verification tools

UVM environment

Job description

Pre-silicon digital verification engineer for mixed signal integrated circuits.

Join an accomplished team at Apple developing custom integrated circuits for Apple’s existing and future product lines. As a member of our mixed signal ASIC team, you will be responsible for verifying complex digital IP’s. You will work with the system architects and digital designers, making block level specifications clear and precise. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks. You will own the creation of the verification testbenches, using formal verification and UVM based simulation. Then you will build the testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.

You will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug free designs on the first tapeout. In addition to traditional digital circuit simulation, you will have the opportunity to learn and use other verification techniques such as formal verification, digital mixed signal verification, and analog mixed signal simulation using state-of-the-art tools.

Although the team is small, we supply silicon to most of Apple’s industry leading hardware development teams. We have a close-knit, high performing team ready to ready to mentor engineers entering the mixed signal ASIC development field. Join us in building Apple’s next generation products. Do you want to be a part of building the “surprise and delight” in Apple’s future products?