Power Design Manager: AI/ML ASICs & TPU Innovation

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google Sunnyvale, CA, USA is seeking a Power Design Manager to lead a team of power design engineers focused on ASIC power architecture and optimization for TPU systems. You will own complex projects from concept through execution, driving low-power RTL designs and cross-functional collaboration across IP and chip vendors.

This role emphasizes hands-on architecture, power modeling, and solving open-ended power and performance challenges in a fast-paced AI hardware environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• 10 years of experience with ASIC or SoC design.
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Responsibilities

• Manage a power design team responsible for power architecture, power optimization and system power integration.
• Lead an experienced team, define processes to improve power efficiency of TPU designs.
• Contribute to design power modeling and drive convergence to power targets.
• Investigate and deploy architectural and microarchitectural power optimization techniques for low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures.

Skills

Power design

Power modeling

Power architecture

Power reduction methodologies

Problem solving under ambiguity

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's or PhD in Electrical Engineering, Computer Engineering, or Computer Science

Job description

Google Sunnyvale, CA, USA is seeking a Power Design Manager to lead a team of power design engineers focused on ASIC power architecture and optimization for TPU systems. You will own complex projects from concept through execution, driving low-power RTL designs and cross-functional collaboration across IP and chip vendors.

This role emphasizes hands-on architecture, power modeling, and solving open-ended power and performance challenges in a fast-paced AI hardware environment.