Senior ASIC Power Architect for ML Accelerators

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Job summary

Google LLC in Sunnyvale, CA, is seeking a Staff ASIC Power Engineer for ML accelerators. You will shape AI/ML hardware acceleration by driving power-aware TPU architectures and implementing robust power models.

You will lead power optimization efforts across pre- and post-silicon phases, collaborating with software and system teams to meet dynamic power targets and improve overall efficiency of Google's TPUs.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in design or architecture (e.g., logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Responsibilities

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low‑power RTL designs.
• Collaborate with cross‑functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Own the execution and delivery of complex technical projects end‑to‑end, while being the technical lead of an experienced power team.

Skills

Power design

Power modeling

Power architecture

Power reduction

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Job description

Google LLC in Sunnyvale, CA, is seeking a Staff ASIC Power Engineer for ML accelerators. You will shape AI/ML hardware acceleration by driving power-aware TPU architectures and implementing robust power models.

You will lead power optimization efforts across pre- and post-silicon phases, collaborating with software and system teams to meet dynamic power targets and improve overall efficiency of Google's TPUs.