Senior ASIC Power Architect for ML Accelerators

Google; Sunnyvale (CA); Presencial; USD 192 000 - 278 000; Tempo integral

Resumo da oferta

Google is shaping the future of AI/ML hardware acceleration through TPU power design, delivering efficient, scalable silicon for world‑class AI workloads. You will drive power modeling, implement novel optimization techniques, and contribute to RTL low‑power practices within a cutting‑edge TPU architecture team.

You will collaborate across hardware and software groups to meet dynamic power targets and deliver robust, power‑aware designs, enabling high‑performance AI systems at scale.

Qualificações

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in design or architecture (e.g., logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Responsabilidades

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low‑power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Own the execution and delivery of complex technical projects end-to-end, while being the technical lead of an experienced power team.

Conhecimentos

Bachelor's degree (see education)

Experience in design/architecture

Power design/architecture/metrics

Formação académica

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Descrição da oferta de emprego

Google is shaping the future of AI/ML hardware acceleration through TPU power design, delivering efficient, scalable silicon for world‑class AI workloads. You will drive power modeling, implement novel optimization techniques, and contribute to RTL low‑power practices within a cutting‑edge TPU architecture team.

You will collaborate across hardware and software groups to meet dynamic power targets and deliver robust, power‑aware designs, enabling high‑performance AI systems at scale.