Silicon Engineering Manager - AI/ML TPU & EMIR

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Bonus target 20%

Equity

Benefits package

Job summary

Google Sunnyvale is seeking a Silicon Engineering Manager for EMIR and Power Grid within AI/ML hardware acceleration. You will lead the EMIR and power integrity teams, shaping budgets, signoff methodologies, and flow improvements for block to full-chip designs, including proactive floorplanning and IP integration.

You will partner with physical design, circuits, technology, and packaging teams to deliver robust ASICs/SoCs, drive tool evaluations, and advance novel power delivery solutions across

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CE/CS.
• 10 years in physical design with power delivery and advanced nodes.
• 3 years in people management and mentoring.
• Experience with EMIR budgeting, analysis, and signoff.
• Familiarity with EMIR tools RedHawk, Totem, Voltus.

Responsibilities

• Direct strategy and leadership for the power grid distribution and integrity team.
• Oversee EMIR analysis from block to full-chip level with signoff checks.
• Collaborate with PD, STA, packaging, and circuits to set EMIR budgets and signoff methods.
• Work with internal groups and vendors to define EMIR tool capabilities.
• Grow the team through development plans and staffing initiatives.

Skills

Power/physical design experience

People management

EMIR experience

EMIR tools

Power grid design

Education

Bachelor's degree in Electrical/CS/CE or related

Master's/PhD preferred (Electrical/CE/CS)

Tools

RedHawk

Totem

Voltus

Job description

Google Sunnyvale is seeking a Silicon Engineering Manager for EMIR and Power Grid within AI/ML hardware acceleration. You will lead the EMIR and power integrity teams, shaping budgets, signoff methodologies, and flow improvements for block to full-chip designs, including proactive floorplanning and IP integration.

You will partner with physical design, circuits, technology, and packaging teams to deliver robust ASICs/SoCs, drive tool evaluations, and advance novel power delivery solutions across