TPU Silicon Design Manager – RTL & ML Accelerators

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC seeks a Silicon Design Manager to shape AI/ML hardware acceleration, driving TPU architecture and verifying complex digital designs. You will lead RTL design engineers in Sunnyvale, delivering high-performance, power-efficient silicon for Google's AI workloads.

You will collaborate with architects, timing, physical design, testing, and software teams to align feasibility with product goals, emphasizing leadership and scalable hardware expertise.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Responsibilities

• Lead, mentor, and manage RTL Design Engineers on IP development for Compute Cores.
• Provide technical leadership and model best design practices (micro-architecture, reviews, design methodology).
• Serve as primary design contact; participate with Architecture and System Design on IP area estimation and power optimization.
• Collaborate with Verification, DFt, Physical Design, and Software to plan designs and report status.
• Drive improvements in design methodologies, processes, and quality control measures.

Skills

Chip design experience

SystemVerilog

People leadership

Computer architecture

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

ASIC Verification

Design For Testing (DFT)

Synthesis

Static Timing Analysis (STA)

Physical Design

Job description

Google LLC seeks a Silicon Design Manager to shape AI/ML hardware acceleration, driving TPU architecture and verifying complex digital designs. You will lead RTL design engineers in Sunnyvale, delivering high-performance, power-efficient silicon for Google's AI workloads.

You will collaborate with architects, timing, physical design, testing, and software teams to align feasibility with product goals, emphasizing leadership and scalable hardware expertise.