Physical Design Lead - RTL to GDSII for AI ASICs

Cisco Systems, Inc; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Physical Design Engineer for Silicon One Optics. You will lead end-to-end RTL-to-GDSII physical design across advanced nodes, including floorplanning and signoff to ensure first-pass silicon success.

Join a cross-functional team working with RTL, Analog, DFT, Packaging, and CAD to scale digital flows using Python, TCL, and Shell scripting, while pushing QoR and faster turnaround in a high-performance data-center networking environment.

Qualifications

• Bachelor's degree with 8+ years, or Master's with 6+ years, or PhD with 3+ years in related field.
• Experience in ASIC/SoC physical design and implementation in advanced tech nodes.
• Hands-on experience with full physical design flow at block or chip level.
• Experience with EDA tool flows, back-end sign-off criteria, and automation using Python, TCL, and Shell scripts.

Responsibilities

• Lead end-to-end RTL-to-GDSII physical design across advanced nodes.
• Drive hierarchical floorplanning, complex macro placement, and signoff (STA, IR/EM, PV).
• Architect and scale digital implementation flows with TCL/Python automation to improve QoR and turnaround times.
• Collaborate with RTL, Analog, DFT, Packaging, and CAD teams to resolve cross-domain bottlenecks.

Skills

ASIC/SoC design

Physical design

EDA flows & sign-off

Python/TCL/Shell scripting

Tools

EDA tools

Job description

Cisco Systems, Inc. is seeking a Physical Design Engineer for Silicon One Optics. You will lead end-to-end RTL-to-GDSII physical design across advanced nodes, including floorplanning and signoff to ensure first-pass silicon success.

Join a cross-functional team working with RTL, Analog, DFT, Packaging, and CAD to scale digital flows using Python, TCL, and Shell scripting, while pushing QoR and faster turnaround in a high-performance data-center networking environment.