Packaging Design Engineer: Substrate Layout & Interconnects

Intel; Phoenix (AZ); On-site; USD 105,650 - 149,150; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Vacation time

Job summary

A leading technology firm is seeking a Silicon Packaging Design Engineer in Phoenix, Arizona. This role involves end-to-end development of substrate designs, collaboration with silicon and hardware teams, and ensuring optimal cost efficiency and manufacturability. Ideal candidates will have a relevant Bachelor's or Master's degree and 1+ years of experience in microelectronic package design or PCB layout. Responsibilities include driving design layout, analyzing data, and ensuring quality standards are met. Competitive compensation and benefits are offered.

Qualifications

• Bachelors with 1+ years of experience or Master’s degree with 6 months of experience.
• Experience with microelectronic package or PCB layout design.
• Familiarity with package design tools.

Responsibilities

• Drive layout and routing of package designs.
• Analyze data for manufacturability and performance.
• Collaborate with cross-functional teams.

Skills

Microelectronic package design

PCB layout design

Data analysis

Education

Bachelor's or Master's in Electrical Engineering, Mechanical Engineering, or Material Sciences

Tools

Siemens Xpedition

Cadence Allegro Package Design

AutoCAD

SolidWorks

Job description

A leading technology firm is seeking a Silicon Packaging Design Engineer in Phoenix, Arizona. This role involves end-to-end development of substrate designs, collaboration with silicon and hardware teams, and ensuring optimal cost efficiency and manufacturability. Ideal candidates will have a relevant Bachelor's or Master's degree and 1+ years of experience in microelectronic package design or PCB layout. Responsibilities include driving design layout, analyzing data, and ensuring quality standards are met. Competitive compensation and benefits are offered.