Senior Packaging Design Architect — Substrate & IC

Intel Corporation; Phoenix (AZ); Hybride; USD 221 000 - 312 000; Plein temps

Résumé du poste

Intel Corporation seeks an experienced Packaging Design Architect to drive end-to-end substrate design from concept through tape-out, and to implement physical layout and routing of the package design.

You'll collaborate with silicon and hardware teams to optimize silicon-package-board performance, define substrate design rules, and resolve DRCs while documenting progress in the product lifecycle system.

Qualifications

• Ph.D./master in EE, chemical, mechanical engineering or material science.
• 10+ years with deep knowledge in package, PCB design or IC digital design.
• Strong design, analysis and problem-solving skills.

Responsabilités

• Drive end-to-end substrate design from concept through tape-out.
• Implement physical layout and routing of the package design.
• Perform substrate fit and routing studies to optimize design and cost.
• Collaborate with silicon and hardware teams to optimize performance and pinout.
• Define design rules and resolve DRCs; document in lifecycle system.

Formation

Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science

Outils

Mentor Cadence tools

Cadence Allegro platform

Mentor Xpedition platform

SPICE/Ansys tools

Description du poste

Intel Corporation seeks an experienced Packaging Design Architect to drive end-to-end substrate design from concept through tape-out, and to implement physical layout and routing of the package design.

You'll collaborate with silicon and hardware teams to optimize silicon-package-board performance, define substrate design rules, and resolve DRCs while documenting progress in the product lifecycle system.