Neuromorphic SoC DFX Lead — Test & Validation

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel Corporation's Neuromorphic Computing Lab seeks an experienced DFT/SoC engineer to architect DFT at the SoC level, covering synchronous and asynchronous designs. You will drive sc an insertion, compression and ATPG, and collaborate to advance DFT/DFD/DFM for manufacturability.

You will lead flow development across EDA, RTL, and emulation to deliver test vectors, own IP/SoC scan constructs, and support post-silicon debugging with a hybrid US work model.

Qualifications

• Bachelors and 6+ years OR Masters and 4+ years of hands-on DFT experience from architecture to silicon bring-up.
• 6+ years architecting the DFT stack including scan insertion, compression and ATPG vector generation.
• 4+ years direct ownership of IP and SoC-level scan constructs (e.g. boundary scan, TAP, BIST/MBIST).
• 1 year of debugging post-silicon and driving circuit changes for testability and reliability improvements.

Responsibilities

• Architect a complete DFT solution at the SoC level, compiling requirements of both synchronous and asynchronous designs.
• Lead the flow-development for scan-insertion and compression at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors.
• Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
• Lead silicon power-on, enabling tester content, debugging failures and maintaining any tools/flows that are developed.

Skills

DFT architecture

SystemVerilog

Pre-silicon verification

IP/SoC ownership

Troubleshooting

Education

Bachelor's in Electrical Engineering or related

Master's in a related field

Tools

JTAG/Boundary Scan

ATPG tooling

EDA toolchain

Job description

Intel Corporation's Neuromorphic Computing Lab seeks an experienced DFT/SoC engineer to architect DFT at the SoC level, covering synchronous and asynchronous designs. You will drive sc an insertion, compression and ATPG, and collaborate to advance DFT/DFD/DFM for manufacturability.

You will lead flow development across EDA, RTL, and emulation to deliver test vectors, own IP/SoC scan constructs, and support post-silicon debugging with a hybrid US work model.