Senior DFT Architect for AI ASICs (Onsite)

Neurophos, Inc.; Austin, Northern (TX, KY); Hybrid; USD 150,000 - 230,000; Full time

Benefits offered by this job

100% health plan premiums coverage

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Personalized benefits

Job summary

Neurophos, Inc. is hiring a DFT Architect to own design-for-test for a cutting-edge ASIC. You will define the DFT strategy for the full chip, own coverage signoff, and collaborate with RTL and analog/physical teams to build testability in from day one.

This is the first dedicated DFT hire and includes leading the test program through post-silicon phases. You will develop functional test vectors, architect on-die memory testing, and deploy a scalable DFT flow with near-100% coverage goals across

Qualifications

• 8 to 15 years in DFT with ownership of scan, ATPG, and MBIST.
• Architect-level experience on a large digital ASIC with full-chip DFT strategy.
• Experience developing functional test vectors to augment coverage.
• Tapeout experience on a complex compute ASIC.

Responsibilities

• Own DFT architecture and test control design for multiple ASIC devices using ATPG,MBIST and JTAG.
• Define DFT strategy and signoff, and drive testability from RTL to post-silicon.
• Collaborate with RTL and physical design to incorporate testability early.
• Develop system-level wafer and package DFT plans across product Phases.
• Create integrated DFT development flow with metrics for rapid analysis.
• Lead coverage assessment decisions and justify gaps when needed.
• Specify functional test vectors to augment structural coverage.
• Define analog test requirements in collaboration with the analog team.
• Handoff to post-silicon test program with operations and packaging teams.
• Deliver and deploy production-level test plans to OSAT.

Skills

DFT architecture

ATPG

MBIST

ASIC test design

Tools

Cadence toolchain

Silicon photonics test

Post-silicon test programs

Job description

Neurophos, Inc. is hiring a DFT Architect to own design-for-test for a cutting-edge ASIC. You will define the DFT strategy for the full chip, own coverage signoff, and collaborate with RTL and analog/physical teams to build testability in from day one.

This is the first dedicated DFT hire and includes leading the test program through post-silicon phases. You will develop functional test vectors, architect on-die memory testing, and deploy a scalable DFT flow with near-100% coverage goals across