Neuromorphic Silicon DFX Lead for SoC Testing

Intel; Austin (TX); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health plan

Retirement plan

Paid vacation

Job summary

Intel's Neuromorphic Computing Lab in Hillsboro, Oregon, is seeking a senior product development engineer to lead the DFT/DFX strategy for our neuromorphic silicon program. You will architect test, debug, and reliability solutions enabling high-volume production for innovative asynchronous circuits and advanced integration technologies.

Collaborating with design teams and circuit experts, you will define test strategies, improve fault coverage, and drive manufacturing readiness for high-volume

Qualifications

• Bachelor’s and 6+ years OR Master’s and 4+ years of hands-on DFT experience.
• 6+ years of experience architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
• 4+ years of direct ownership of IP and SoC-level scan constructs, e.g. boundary scan (JTAG), TAP, BIST/MBIST.
• 1 year of experience in debugging post-silicon and driving circuit changes for testability and reliability improvements.

Responsibilities

• Architect a complete DFT solution at the SoC level, compiling the requirements of both synchronous and asynchronous designs.
• Lead the flow-development for scan-insertion and compression at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors and validate them pre-silicon.
• Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
• Lead silicon power-on, enabling tester content, debugging failures and maintaining any tools/flows that are developed.

Skills

DFT experience

IP/SoC ownership

Debug post-silicon

Asynchronous architectures

Testability improvements

Education

Bachelor’s degree in EE / CS or related field

6+ years DFT hands-on experience OR Master’s +4 years

Tools

SystemVerilog

System-C

ATPG vector generation

JTAG / boundary scan

Job description

Intel's Neuromorphic Computing Lab in Hillsboro, Oregon, is seeking a senior product development engineer to lead the DFT/DFX strategy for our neuromorphic silicon program. You will architect test, debug, and reliability solutions enabling high-volume production for innovative asynchronous circuits and advanced integration technologies.

Collaborating with design teams and circuit experts, you will define test strategies, improve fault coverage, and drive manufacturing readiness for high-volume