Neuromorphic SoC DFT/DFX Lead — Hybrid Role

Intel Corporation; Phoenix (AZ); Hybrid; USD 161,000 - 269,000; Full time

Job summary

Intel's Neuromorphic Computing Lab in Hillsboro, Oregon, leads innovative DFT/DFX strategies for Loihi neuromorphic silicon, driving test methodologies for asynchronous designs and high-volume production.

As the DFT/DFX lead, you will define test strategies, build scalable frameworks across RTL, emulation, and EDA tools, collaborate with layout and circuit experts, and push manufacturing readiness while exploring agentic tools and new design techniques.

Qualifications

• Bachelor's or Master's with 4+ years DFT experience from architecture to silicon bring-up.
• Experience with DFT stack: scan insertion, compression, ATPG vector generation.
• IP/SoC-level scan constructs ownership (JTAG, TAP, BIST/MBIST).
• Debug post-silicon and drive testability/reliability improvements.

Responsibilities

• Architect complete DFT at SoC level for synchronous and asynchronous designs.
• Lead scan-insertion flow development and compression at partition and SoC levels.
• Build scalable framework across EDA tools, RTL and emulation models to generate high-quality test vectors.
• Collaborate with designers to drive DFT/DFD/DFM features for manufacturing readiness (HVM).
• Lead silicon power-on, tester content, debugging failures and maintain tools/flows.

Skills

DFT Architecture

ATPG Vector Gen

IP/SoC Testability

Boundary Scan

Asynchronous Design

Tool Flows

JTAG

Education

Bachelor's degree in engineering

Master's degree in engineering

Tools

SystemVerilog

System-C

RTL/Emulation Models

EDA Tools

AI Tool Flows

Job description

Intel's Neuromorphic Computing Lab in Hillsboro, Oregon, leads innovative DFT/DFX strategies for Loihi neuromorphic silicon, driving test methodologies for asynchronous designs and high-volume production.

As the DFT/DFX lead, you will define test strategies, build scalable frameworks across RTL, emulation, and EDA tools, collaborate with layout and circuit experts, and push manufacturing readiness while exploring agentic tools and new design techniques.