Neuromorphic SoC DFT/DFX Lead — Hybrid, High-Impact

Intel; Santa Clara (CA); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel is seeking a senior product development engineer to lead the DFT/DFX strategy for their neuromorphic silicon program in a hybrid setting. You will architect test, debug, and reliability solutions for high-volume production of Loihi-related hardware, partnering with design architects and circuit experts to drive DFT/DFM features.

The role requires building innovative test methodologies for asynchronous circuits and leveraging agentic tools for development and debugging, with a focus on

Qualifications

• Bachelor degree with 6+ years or Master with 4+ years DFT experience.
• Experience architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
• 1 year of debugging post-silicon and driving circuit changes for testability and reliability improvements.

Responsibilities

• Architect a complete DFT solution at the SoC level for synchronous and asynchronous designs.
• Lead flow-development for scan-insertion and compression at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors pre-silicon.
• Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness for high-volume manufacturing.
• Lead silicon power-on, enable tester content, debugging failures and maintaining tools/flows.

Skills

DFT/DFX engineering

SoC DFT design

JTAG boundary scan

ATPG vector generation

Post-silicon debugging

Asynchronous design

AI tool flows

Education

Bachelor's degree + 6+ years

Master's degree + 4+ years

Tools

JTAG boundary scan

TAP

BIST/MBIST

Job description

Intel is seeking a senior product development engineer to lead the DFT/DFX strategy for their neuromorphic silicon program in a hybrid setting. You will architect test, debug, and reliability solutions for high-volume production of Loihi-related hardware, partnering with design architects and circuit experts to drive DFT/DFM features.

The role requires building innovative test methodologies for asynchronous circuits and leveraging agentic tools for development and debugging, with a focus on