Neuromorphic DFX Lead - SoC Test & Validation (Hybrid)

Intel Corporation; Phoenix (AZ); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel Corporation's Neuromorphic Computing Lab is seeking a senior product development engineer to lead the DFT/DFX strategy for the Loihi neuromorphic silicon program. You will define test methodologies for high-volume production and partner with design architects to enable robust pre-silicon verification.

This role focuses on architecting a complete DFT solution at the SoC level, driving fault coverage, and delivering scalable flows across EDA tools, RTL, and emulation to support manufacturing

Qualifications

• Bachelor's degree with 6+ years or Master's with 4+ years in DFT from architecture to silicon bring-up.
• 6+ years architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
• 1 year debugging post-silicon and driving circuit changes for testability and reliability.

Responsibilities

• Architect a complete DFT solution at the SoC level, for synchronous and asynchronous designs.
• Lead flow-development for scan-insertion and compression at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors and validate them pre-silicon.
• Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
• Lead silicon power-on, enabling tester content, debugging failures and maintaining any tools/flows that are developed.

Skills

DFT architecture

Post-silicon debugging

ASIC/AI accelerator design

DLCP / die-level cherry picking

SystemVerilog

System-C

ATPG vector generation

Asynchronous circuits

AI tool flows

test time reduction on ATE

Education

Bachelor's degree

Master's degree

Tools

EDA tools

Job description

Intel Corporation's Neuromorphic Computing Lab is seeking a senior product development engineer to lead the DFT/DFX strategy for the Loihi neuromorphic silicon program. You will define test methodologies for high-volume production and partner with design architects to enable robust pre-silicon verification.

This role focuses on architecting a complete DFT solution at the SoC level, driving fault coverage, and delivering scalable flows across EDA tools, RTL, and emulation to support manufacturing