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Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.
Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.
Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.
Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.