DFT Engineer I – SoC Test & Debug

Cadence Design Systems

Cary (NC)

On-site

USD 89,000 - 165,000

Full time

3 days ago
Be an early applicant
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

Paid vacation
401(k) plan
Employee stock purchase plan
Medical, dental and vision plans
And more

Job summary

Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.

Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.

Qualifications

  • BS degree and at least 3 years of hands-on experience in SoC DFT.
  • Strong expertise in SCAN, ATPG, MBIST.
  • Experience with pre-silicon validation and post-silicon debug.
  • Ability to collaborate with RTL, verification, physical design and operations teams.

Responsibilities

  • Define and implement SoC level DFT architecture for large and complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
  • Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis and yield learning.
  • Collaborate with RTL, verification, physical design and operation teams.

Skills

SCAN
ATPG
MBIST
Pre-silicon validation
Post-silicon debug
Cross-functional teamwork
Scripting (TCL, Python, Perl)

Education

Bachelor's degree

Job description

Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.

Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

DFT Engineer
DFT Engineer

MatchPoint • San Francisco (CA)

On-site
USD 120,000 - 180,000
DFT Engineer
DFT Engineer

Retym, Inc • Austin (TX)

On-site
USD 100,000 - 130,000
DFT Engineers
DFT Engineers

Prime Hiring Solutions • Santa Clara (CA)

On-site
USD 130,000 - 190,000
Prinicipal DFT Engineer
Prinicipal DFT Engineer

Celero Communications • Irvine (CA)

On-site
USD 120,000 - 190,000
DFT Design Engineer - SoC Test & MBIST Expert
DFT Design Engineer - SoC Test & MBIST Expert

Cadence Design Systems • Austin (TX)

On-site
USD 90,000 - 120,000
DFT Engineer
DFT Engineer

Select Minds LLC • Lansing (MI)

On-site
USD 120,000 - 190,000
Day-1 Onsite
Competitive salary
Opportunity for advancement
DFT Engineer
DFT Engineer

QFocus Technologies LLC • Sunnyvale (CA), Northern (KY)

On-site
USD 140,000 - 210,000
DFT Engineer
DFT Engineer

Quest Global • Santa Clara (CA)

On-site
USD 140,000 - 190,000
DFT Design Engineer for SoC RTL & Test Innovation
DFT Design Engineer for SoC RTL & Test Innovation

Intel • Austin (TX)

On-site
USD 141,910 - 200,340
Stock bonuses
Health benefits
Paid time off
DFT Engineer - SoC/ASIC Test & Validation
DFT Engineer - SoC/ASIC Test & Validation

MatchPoint • San Francisco (CA)

On-site
USD 120,000 - 180,000