Memory Subsystem RTL Engineer for High-Speed AI SoC

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Velaura AI, Inc. is seeking an RTL Engineer to build a next-generation Physical AI SoC, focusing on a high-speed, low-power memory subsystem.

You will own large portions of the memory design, collaborate with architects, verification, and memory IP partners, and drive architectural decisions to deliver production silicon. You will work closely with software teams to define interfaces, perform timing closure, and optimize for performance and power while ensuring reliability and scalability across

Qualifications

• Must have hands-on RTL design for complex digital systems.
• Experience integrating memory controller with memory PHY including DFI interfaces.
• Strong knowledge of high-speed memory technologies and power-state behavior.

Responsibilities

• Design, implement, and optimize RTL for the memory subsystem of the SoC.
• Own memory controller and PHY integration, including training flows and bring-up hooks.
• Drive high-speed, low-power memory path design with timing closure and DVFS interactions.
• Collaborate with software to define hardware interfaces and performance-critical interactions.
• Analyze bottlenecks and propose architectural improvements.
• Optimize for performance, power, area, and reliability (ECC, error reporting).
• Work with verification, physical design, and memory IP vendors throughout the cycle.

Skills

RTL design ownership

Memory subsystem design

Verilog/SystemVerilog

DFI integration

Performance optimization

Job description

Velaura AI, Inc. is seeking an RTL Engineer to build a next-generation Physical AI SoC, focusing on a high-speed, low-power memory subsystem.

You will own large portions of the memory design, collaborate with architects, verification, and memory IP partners, and drive architectural decisions to deliver production silicon. You will work closely with software teams to define interfaces, perform timing closure, and optimize for performance and power while ensuring reliability and scalability across