RTL Lead for Physical AI Compute SoC

Velaura AI, Inc.; Santa Clara (CA); Hybrid; USD 200,000 - 300,000; Full time

Benefits offered by this job

Medical, dental, and vision coverage

Paid time off

Flexible work arrangements

Professional development opportunities

Equity compensation

Job summary

Velaura is seeking an experienced RTL Lead to drive the implementation of our next-generation Physical AI SoC. The role blends architectural influence with hands-on technical leadership, collaborating with system architects, AI architects, performance modelers, and software engineers to turn innovative concepts into production-quality silicon.

You will mentor engineers, shape design methodologies, and oversee RTL across compute engines, memory subsystems, interconnects, and system infrastructure

Qualifications

• Strong RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators, networking devices, or related systems.
• Deep understanding of digital design fundamentals and microarchitecture.
• Experience with Verilog/SystemVerilog and modern RTL development methodologies.
• Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement.
• Experience balancing performance, power, area, and design complexity.
• Proven ability to drive complex technical projects from concept through silicon bring-up.
• Experience with hardware/software co-design and performance optimization across the full system stack.
• Familiarity with AI runtimes, operating systems, firmware, drivers, or other system software layers is highly desirable.

Responsibilities

• Lead RTL development across key portions of the Velaura SoC.
• Collaborate with architects to translate system requirements into robust microarchitectures.
• Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture.
• Partner closely with software teams to define programming models, execution flows, memory hierarchies, and performance-critical interfaces.
• Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure.
• Develop high-quality, power-efficient, and scalable RTL implementations.
• Conduct architecture and RTL reviews to ensure performance, power, and area goals are achieved.
• Work closely with performance modeling, verification, physical design, and software teams throughout the development cycle.
• Help establish engineering processes and design methodologies as the organization grows.
• Mentor and develop other RTL engineers.

Skills

RTL design experience

SoC architectures

Verilog/SystemVerilog

microarchitecture

hardware/software co-design

performance optimization

system-level tradeoffs

mentoring engineers

digital design fundamentals

memory systems/interconnect

Job description

Velaura is seeking an experienced RTL Lead to drive the implementation of our next-generation Physical AI SoC. The role blends architectural influence with hands-on technical leadership, collaborating with system architects, AI architects, performance modelers, and software engineers to turn innovative concepts into production-quality silicon.

You will mentor engineers, shape design methodologies, and oversee RTL across compute engines, memory subsystems, interconnects, and system infrastructure