RTL Power Engineer for SoC DVFS

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking an experienced RTL Engineer to help build the next generation Physical AI SoC.

You will own the power management of the chip, work with architects, software and verification teams, and deliver silicon that meets performance within power budgets. You will design on-chip power hardware, temperature control loops, and DVFS-based power state management, while collaborating across RTL, emulation and silicon to provide telemetry and visibility into power and thermal

Qualifications

• Strong grasp of the physics and electrical engineering behind average power, peak current, thermal behavior and voltage droop, and of how these concepts relate while remaining independent.
• Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops.
• Understanding of di/dt, IR drop and power delivery network behavior, and their impact on timing margin.
• Experience with clock and reset architecture including clock gating, PLL management and reset sequencing.
• Working knowledge of Verilog or SystemVerilog and modern RTL design methodology.
• Experience with power estimation and analysis flows from RTL through gate level.
• Strong debugging and problem solving skills across hardware and software boundaries.
• BS or higher in Electrical Engineering, Computer Engineering or a related field.

Responsibilities

• Design the on chip power management hardware for the Velaura SoC including digital power meters, activity monitors and throttlers.
• Design hardware and software control loops around temperature sensors that hold the die under a defined thermal limit.
• Design controls that keep the design under defined activity and average power limits as well as instantaneous di/dt limits.
• Work with architects, physical design and package teams on voltage droop behavior, power delivery and adaptive clocking response.
• Own clock and reset architecture including clock gating, PLL programming and management, and reset sequencing across power domains.
• Define and implement power state management including DVFS, power domains, retention and low power flows.
• Correlate power estimates across RTL, emulation and silicon, and build the telemetry that makes power and thermal behavior visible in the field.
• Work with firmware and software teams on the interfaces, policies and telemetry that drive power and thermal management.

Skills

RTL design

Verilog/SystemVerilog

Power management

Clock/reset architecture

Hardware debugging

Education

BS in Electrical/Computer Engineering

Tools

PowerArtist

PrimePower

Joules

Job description

Velaura AI, Inc. is seeking an experienced RTL Engineer to help build the next generation Physical AI SoC.

You will own the power management of the chip, work with architects, software and verification teams, and deliver silicon that meets performance within power budgets. You will design on-chip power hardware, temperature control loops, and DVFS-based power state management, while collaborating across RTL, emulation and silicon to provide telemetry and visibility into power and thermal