Senior RTL/SoC Design Engineer for AI & In-Memory IP

TetraMem - Accelerate The World; San Jose (CA); On-site; USD 110,000 - 300,000; Full time

Job summary

TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs.

You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout readiness while developing reusable IPs for AI and in-memory computing.

The role includes mentoring junior engineers, contributing to design reviews, and staying current with RTL methodologies to improve product quality.

Qualifications

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design.
• Experience with Verilog and SystemVerilog.
• Experience with pre-layout and post-layout simulation.
• Familiarity with AMBA APB/AXI protocol.
• Familiarity with RISC/Arm or other core architectures.
• Ability to lead architecture and provide technical leadership.
• Startup environment experience preferred.

Responsibilities

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
• Integrate and validate IP blocks within the larger system for seamless functionality.
• Conduct PPA analysis to optimize design trade-offs.
• Collaborate with backend team on RTL coding, implementation, and synthesis for successful tapeout.
• Develop and maintain reusable internal IPs for AI and/or in-memory computing.
• Provide support for Post-Si testing and validation, diagnosing issues to ensure product quality.
• Mentor junior engineers and share best practices to foster growth.
• Contribute to design reviews and cross-functional discussions to enhance performance and reliability.
• Stay current with RTL design trends and innovative techniques to improve quality.
• Collaborate with software, architecture, and verification teams for cohesive development.

Skills

RTL design

Verilog/SystemVerilog

VCS/Verdi

Pre/post-layout sim

AMBA AXI/APB

Arm/RISC cores

Technical leadership

Cross-functional teamwork

Mentoring

Education

MS or PhD in Electrical Engineering

Tools

VCS

Verdi

Synthesis tools

Job description

TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs.

You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout readiness while developing reusable IPs for AI and in-memory computing.

The role includes mentoring junior engineers, contributing to design reviews, and staying current with RTL methodologies to improve product quality.