Senior RTL Architect: Memory Subsystem for AI Chips

Kindredventures; Palo Alto (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI-driven memory subsystem RTL design for production silicon. You will shape the microarchitecture, define DDR/HBM controller interfaces, and drive high-bandwidth, low-latency memory paths for ML workloads.

Collaborating with DV, SW, and ML teams, you will refine specs, validate timing, and prototype on FPGA platforms while advancing power and area targets for next‑gen accelerators.

Qualifications

• Degree in Electrical/Computer Engineering or related field.
• 5+ years RTL design; 10+ preferred with memory subsystems tapeout.
• Deep familiarity with JEDEC memory standards (DDR5/LPDDR5X, HBM).
• Hands-on memory controller design with schedulers and ECC/RAS.
• Synthesis, timing constraints, and clock domain crossings experience.
• Strong Python for design automation and regression.

Responsibilities

• Own the memory subsystem RTL end-to-end from design to synthesis.
• Design memory controllers (DDR/HBM) and scheduling policies.
• Architect memory hierarchy and near-memory accelerators.
• Develop and maintain RTL infra and verification collaboration.
• Work with DV, SW, and ML teams to refine specs and timing.
• Support FPGA prototyping and early validation on Xilinx platforms.

Skills

RTL design

SystemVerilog

Python

Synthesis

Timing closure

Memory subsystem

PPA ownership

Regression infrastructure

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Xilinx Vivado

DDR/LPDDR/HBM controllers

FPGA prototyping

JEDEC standards knowledge

Job description

Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI-driven memory subsystem RTL design for production silicon. You will shape the microarchitecture, define DDR/HBM controller interfaces, and drive high-bandwidth, low-latency memory paths for ML workloads.

Collaborating with DV, SW, and ML teams, you will refine specs, validate timing, and prototype on FPGA platforms while advancing power and area targets for next‑gen accelerators.