AI Memory Design Engineer - RTL & Silicon

Micron Technology; Folsom (CA); On-site; USD 175,000 - 309,000; Full time

Job summary

Micron Technology in the United States is seeking a Member of Technical Staff to translate architectural vision into silicon-proven hardware implementations for high-performance memory systems. You will design and review SystemVerilog RTL, optimize area, power, and timing, and document microarchitectures to align cross-team understanding.

The role focuses on scalable memory architectures for AI workloads, balancing performance and reliability across the development lifecycle, with opportunities

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
• Strong experience in digital design and microarchitecture development with ownership of hardware blocks from specification through implementation.
• Proficiency in SystemVerilog and at least one programming language such as C, C++, or Python.

Responsibilities

• Translate architecture requirements into scalable microarchitectures and drive implementation from concept through silicon
• Design, implement, and review SystemVerilog RTL for advanced memory system architectures
• Perform synthesis and early PPA analysis to optimize area, power, and timing
• Develop and maintain microarchitecture documentation that aligns design intent across teams
• Evaluate architectural and implementation tradeoffs to support technical decision-making

Skills

SystemVerilog

Digital design

Microarchitecture

C/C++

Python

Education

Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field

Job description

Micron Technology in the United States is seeking a Member of Technical Staff to translate architectural vision into silicon-proven hardware implementations for high-performance memory systems. You will design and review SystemVerilog RTL, optimize area, power, and timing, and document microarchitectures to align cross-team understanding.

The role focuses on scalable memory architectures for AI workloads, balancing performance and reliability across the development lifecycle, with opportunities