Masters ASIC Packaging Co-op – Design & Yield Impact

AMD

Santa Clara (CA)

Hybrid

USD 34,000 - 44,000

Full time

12 days ago
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Benefits offered by this job

AMD benefits

Job summary

AMD invites motivated Masters candidates to join as an intern or co-op in Santa Clara/San Jose, offering hands-on work on packaging design and development for AMD products. You'll gain experience in substrate, interposer and bump designs, with exposure to test vehicles and probe cards while contributing to design verification and yield improvement.

The program is onsite/hybrid, spanning Spring/Summer and Summer-Fall terms, with opportunities for collaboration across teams and access to AMD

Qualifications

  • Enrolled in a US-based university for a Master’s degree in a related field.
  • Familiar with transmission lines, electric circuits and packaging processes.
  • Experience with package, silicon or PCB design software and scripting languages.
  • Knowledge of data analytics and data visualization tools like PowerBI is a plus.

Responsibilities

  • Assist Package design and Development Eng by prioritizing and optimizing new projects.
  • Learn substrate, interposer, and bump design for AMD products and test vehicles.
  • Support design verification to ensure performance, quality and efficiency.
  • Analyze yield and defect metrics to improve design performance and yield.
  • Evaluate and benchmark packaging materials with partners for cost-effective design.

Skills

Transmission lines
PCB design software
Scripting (Perl/Python/SQL)
Semiconductor theory
Data analytics (PowerBI)

Education

Master's degree in Electrical Engineering / related field

Tools

PowerBI
Package design software
PCB design software

Job description

AMD invites motivated Masters candidates to join as an intern or co-op in Santa Clara/San Jose, offering hands-on work on packaging design and development for AMD products. You'll gain experience in substrate, interposer and bump designs, with exposure to test vehicles and probe cards while contributing to design verification and yield improvement.

The program is onsite/hybrid, spanning Spring/Summer and Summer-Fall terms, with opportunities for collaboration across teams and access to AMD

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