ASIC Packaging Engineer Intern — Design, Yield & Innovation

Advanced Micro Devices; San Jose (CA); Hybrid; USD 34,000 - 48,000; Full time

Benefits offered by this job

Paid internship

Mentorship program

Networking opportunities

Job summary

AMD invites motivated students for an ASIC Package Engineering internship/co-op in the San Jose/Santa Clara area. You will work 40 hours per week in a hybrid or onsite setting across the co-op/intern term, contributing to advanced packaging technologies and test vehicles.

You will gain hands-on experience in substrate, interposer, and bump design, design verification, and yield analysis while collaborating with seasoned engineers.

Qualifications

• Currently enrolled in a US university pursuing a Bachelor’s degree in Electrical Engineering, Engineering Science, Computer Engineering, Mechanical Engineering, or a related field.
• Knowledge of scripting languages (Python, Perl, SQL) and data analytics tools.
• Familiarity with semiconductor packaging concepts and design tools is a plus.

Responsibilities

• Assist in prioritizing and optimizing new packaging projects.
• Support substrate, interposer, and bump design efforts for AMD products and test vehicles.
• Contribute to design verification to ensure performance and quality.
• Analyze yield and defect metrics to improve design yield.
• Evaluate packaging materials and interact with partners to balance cost and performance.

Skills

Python scripting

PowerBI

Data analytics

Team collaboration

Education

Bachelor's degree in Electrical engineering or related field

Tools

Package design software

Si/PCB design software

Job description

AMD invites motivated students for an ASIC Package Engineering internship/co-op in the San Jose/Santa Clara area. You will work 40 hours per week in a hybrid or onsite setting across the co-op/intern term, contributing to advanced packaging technologies and test vehicles.

You will gain hands-on experience in substrate, interposer, and bump design, design verification, and yield analysis while collaborating with seasoned engineers.