Senior SI Engineer – SerDes & Packaging (Hybrid, Equity)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Signal Integrity Engineer to drive high‑speed SerDes channel design across die, package, board, and system interfaces. You will develop SI methodologies for 2.5D/3D packaging and correlate simulations with lab measurements, enabling robust interconnects for HPC and AI workloads.

Join a cross‑functional team, own design guidelines, and push technology boundaries with state‑of‑the‑art tools and automation to scale SI across programs.

Qualifications

• BS, MS, or PhD in Electrical Engineering or equivalent experience.
• 8+ years of industry experience in signal integrity or related hardware development.
• Strong background in electromagnetics, transmission line theory, and high-speed signaling.
• Experience with SerDes design and analysis for packaging and large-scale systems.
• Hands-on experience with industry SI tools (HFSS, SIwave, Sigrity, ADS, HSPICE).
• Experience building and using channel models, S-parameters, IBIS-AMI flows.

Responsibilities

• Lead SI design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces.
• Develop and execute simulation flows for 2.5D/3D packaging with focus on loss, discontinuities, return paths, and crosstalk.
• Build and optimize chip-package-board co-simulation methodologies for HPC and data center systems.
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, and substrates.
• Perform pre- and post-layout SI analysis, create design guidelines, and review layouts for electrical targets.
• Correlate simulation with lab measurements using VNA, TDR, and high-speed oscilloscope to improve model accuracy.
• Work with ASIC, package, board, mechanical, and thermal teams to co-optimize electrical performance.
• Support interface bring-up, debug, margin analysis, and translate learnings into improved methods.
• Automate analysis, data processing, and visualization to scale SI methodology across programs.

Skills

Signal integrity

SerDes design

High-speed interconnect

Electromagnetics

Education

Electrical Engineering degree

Tools

Ansys HFSS

SIwave

Cadence Sigrity

ADS

HSPICE

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Signal Integrity Engineer to drive high‑speed SerDes channel design across die, package, board, and system interfaces. You will develop SI methodologies for 2.5D/3D packaging and correlate simulations with lab measurements, enabling robust interconnects for HPC and AI workloads.

Join a cross‑functional team, own design guidelines, and push technology boundaries with state‑of‑the‑art tools and automation to scale SI across programs.