Lead Digital ASIC Architect for High-Speed Interconnects

Cisco Systems; Carlsbad (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Cisco Systems is seeking a Digital Design Technical Leader for the Silicon One Optics team in California. You will own the full ASIC lifecycle, from RTL design to tapeout, and drive complex digital blocks across CPU subsystems and SoCs.

You will coordinate cross-functional teams in optical interconnects and high-speed IP integration. This role emphasizes architecture definition, power/performance optimization, and end-to-end verification.

Qualifications

• Experience with end-to-end ASIC/SoC design flow.
• Proficient with high-speed SerDes, Ethernet, and D2D PHY IP.
• Strong RTL design and verification background.
• Experience from pre-silicon RTL to GDSII signoff and post-silicon bring-up.

Responsibilities

• Lead end-to-end silicon design contributions from RTL to GDS2 signoff.
• Define digital architectures and high-speed datapaths for 100G/200G/400G interconnects.
• Coordinate verification, IP integration, and QoR metric improvements.
• Support synthesis, DFT, low-power design, and timing closure.
• Collaborate with cross-functional teams to maintain system stability.

Skills

Digital design

FSMs

CPU subsystems

SoC design flow

FPGA validation

SerDes IP

Ethernet

D2D PHY IP

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

GDSII

FPGA prototyping

Simulation tools

Lab hardware

Job description

Cisco Systems is seeking a Digital Design Technical Leader for the Silicon One Optics team in California. You will own the full ASIC lifecycle, from RTL design to tapeout, and drive complex digital blocks across CPU subsystems and SoCs.

You will coordinate cross-functional teams in optical interconnects and high-speed IP integration. This role emphasizes architecture definition, power/performance optimization, and end-to-end verification.