Lead ASIC Digital Design Engineer: High-Speed IP & SoC

Cisco Systems, Inc; Carlsbad (CA); On-site; USD 166,000 - 238,000; Full time

Job summary

Cisco Systems, Inc. is hiring a Digital Design Technical Leader for Silicon One Optics in California. You will own the full ASIC lifecycle, architect digital flows, integrate SerDes/IP, and lead cross‑functional teams across digital, analog, firmware, and physical design.

This role focuses on 100G/200G/400G interconnects, with responsibilities spanning RTL through GDS2, lab validation, and ATE bring‑up, while optimizing power and performance.

Qualifications

• Bachelor’s degree or higher in a related field.
• 8+ years in digital design or SoC development with ASIC flow.
• Experience with high‑speed interfaces (SerDes, Ethernet, D2D).
• Proven ability to lead full ASIC/SoC design lifecycle.
• Strong knowledge of bus protocols (SPI, I2C, AXI) and IP integration.

Responsibilities

• Lead end-to-end silicon design from RTL to tapeout and bring‑up.
• Define digital architectures and integrate high‑speed IPs.
• Drive power, timing, and hardware/firmware trade‑offs.
• Oversee verification, IP integration, and QoR analysis.
• Coordinate with cross‑functional teams to ensure system stability.

Skills

Digital design

ASIC/SoC design

FPGA validation

CPU subsystems

SerDes IP

Ethernet IP

Power budgeting

Education

Bachelor's degree or higher

Tools

GDSII

Verilog

VHDL

EDA tools

FPGA prototyping

Job description

Cisco Systems, Inc. is hiring a Digital Design Technical Leader for Silicon One Optics in California. You will own the full ASIC lifecycle, architect digital flows, integrate SerDes/IP, and lead cross‑functional teams across digital, analog, firmware, and physical design.

This role focuses on 100G/200G/400G interconnects, with responsibilities spanning RTL through GDS2, lab validation, and ATE bring‑up, while optimizing power and performance.