ASIC Digital Design Tech Lead

Cisco Systems; Carlsbad (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Cisco Systems is seeking a Digital Design Technical Leader for the Silicon One Optics team in California. You will own the full ASIC lifecycle, from RTL design to tapeout, and drive complex digital blocks across CPU subsystems and SoCs.

You will coordinate cross-functional teams in optical interconnects and high-speed IP integration. This role emphasizes architecture definition, power/performance optimization, and end-to-end verification.

Qualifications

• Experience with end-to-end ASIC/SoC design flow.
• Proficient with high-speed SerDes, Ethernet, and D2D PHY IP.
• Strong RTL design and verification background.
• Experience from pre-silicon RTL to GDSII signoff and post-silicon bring-up.

Responsibilities

• Lead end-to-end silicon design contributions from RTL to GDS2 signoff.
• Define digital architectures and high-speed datapaths for 100G/200G/400G interconnects.
• Coordinate verification, IP integration, and QoR metric improvements.
• Support synthesis, DFT, low-power design, and timing closure.
• Collaborate with cross-functional teams to maintain system stability.

Skills

Digital design

FSMs

CPU subsystems

SoC design flow

FPGA validation

SerDes IP

Ethernet

D2D PHY IP

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

GDSII

FPGA prototyping

Simulation tools

Lab hardware

Job description

The application window is expected to close on: 01/18/2027

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

As a Digital Design Technical Leader for Silicon One Optics, you won't just be building chips—you will architect the backbone of next-generation optical interconnects. From initial concept to tapeout and post-silicon production, you will own the full ASIC lifecycle and lead cross-functional engineering teams across digital, analog, firmware, and physical design.

In this high-stakes role, you will define digital architectures, spearhead the integration of cutting-edge high-speed IPs (ODSP, D2D IP, SerDes XSR/PAM4), and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. This is your opportunity to drive technical strategy, pioneer breakthrough interconnect innovations, and deliver silicon that powers the future of high-performance computing.

• End-to-End Silicon & Subsystem Design: Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up (FPGA prototyping, lab validation, and ATE) for complex digital blocks and CPU subsystems.
• Architecture & Specification: Translate top-level requirements into high-speed datapath and low-speed control plane block specifications—balancing power, timing, loop dynamics, and hardware/firmware trade-offs.
• Verification & IP Integration: Independently simulate and debug complex design issues, sign off on verification coverage, and support the integration of SerDes and DSP IPs.
• Backend Implementation & Automation: Support synthesis, DFT, low-power design, and timing closure while developing automation scripts to process Quality of Results (QoR) metrics.
• Cross-Functional Collaboration: Partner seamlessly with cross-functional teams to resolve technical design challenges and maintain system stability.

Minimum Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation,
• Prior experience in managing the complete ASIC/SoC design flow
• Prior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and D2D PHY IP.

Preferred Qualifications

• End-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.
• Specification &