Senior ASIC Digital Design Lead — High-Speed Optics

Cisco Systems, Inc; Allentown (Lehigh County); On-site; USD 166,000 - 238,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Digital Design Technical Leader for Silicon One Optics.

You will own the full ASIC lifecycle from concept to tapeout, leading cross-functional digital, analog, firmware, and physical design teams to build 100G/200G/400G silicon photonics. This role emphasizes architecture, IP integration, power/performance optimization, and end-to-end silicon validation, with opportunities to shape next‑gen interconnects and drive pioneering hardware platforms across Cisco’s AI

Qualifications

• Experience leading complete ASIC/SoC design flow.
• Experience with FSMs, CPU subsystems, complex SoCs and FPGA validation.
• Experience with bus protocols (SPI, I2C, AXI) and high-speed SerDes and Ethernet IP.
• Strong leadership and cross-functional collaboration.

Responsibilities

• End-to-End Silicon & Subsystem Design: lead design from RTL through GDS2 signoff and post-silicon bring-up.
• Architecture & Specification: translate requirements into high-speed datapath and low-speed control blocks.
• Verification & IP Integration: simulate, debug, sign-off verification, integrate SerDes and DSP IPs.
• Backend Implementation & Automation: support synthesis, DFT, low-power design, and QoR metric processing.
• Cross-Functional Collaboration: partner with engineering teams to resolve design challenges.

Skills

ASIC/SoC design

FSMs & CPU subsystems

SerDes & Ethernet IP

FPGA prototyping

Synthesis & timing analysis

Education

Bachelor's degree

Master's degree

PhD

Tools

FPGA tools

DFT tools

Synthesis tools

RTL simulators

Job description

Cisco Systems, Inc. is seeking a Digital Design Technical Leader for Silicon One Optics.

You will own the full ASIC lifecycle from concept to tapeout, leading cross-functional digital, analog, firmware, and physical design teams to build 100G/200G/400G silicon photonics. This role emphasizes architecture, IP integration, power/performance optimization, and end-to-end silicon validation, with opportunities to shape next‑gen interconnects and drive pioneering hardware platforms across Cisco’s AI