Lead DFT Architect – 2.5D/3D Test Strategy

Eximietas Design; San Francisco (CA); Hybrid; USD 190,000 - 250,000; Full time

Job summary

Eximietas Design is hiring a seasoned DFT Lead to drive test architecture and silicon implementation for next-generation 2.5D / 3D designs. This is a hands-on technical leadership role for an engineer who has spent a career shipping production silicon and is excited to take on chiplet-, interposer-, and HBM-class complexity.

You will work alongside design, verification, packaging, and post-silicon teams to define testability strategy end-to-end — from RTL DFT insertion through pattern

Qualifications

• 10–15 years of hands-on DFT engineering experience.
• Production silicon tapeout in lead role.
• ATPG expertise with Synopsys TetraMAX, Mentor Tessent, or Cadence Modus.
• Deep knowledge of scan compression, MBIST, LBIST, and BIST.
• Experience with JTAG/Boundary Scan and IEEE 1149.x/1687.
• Experience with 2.5D/3D design and chiplet interconnect test.
• Strong fault models and coverage analysis background.
• Strong debugging and problem-solving in silicon labs.
• Clear communication to align teams and stakeholders.

Responsibilities

• Define and own the DFT architecture for advanced packaging.
• Lead ATPG strategy and implementation using specified tools.
• Architect and integrate scan/MBIST/LBIST/BIST across SoCs.
• Design and validate JTAG/Boundary Scan and IEEE networks.
• Partner with packaging and physical design to meet DFT needs.
• Support post-silicon validation and ATE bring-up.
• Mentor and grow DFT engineering capability.
• Interface with stakeholders to communicate DFT plans and risks.

Skills

DFT engineering

ATPG expertise

Scan compression

MBIST/LBIST/BIST

JTAG/Boundary Scan

2.5D/3D design knowledge

Fault models & coverage

Debug & problem solving

Clear communicator

Tools

Synopsys TetraMAX

Mentor Tessent

Cadence Modus

Job description

Eximietas Design is hiring a seasoned DFT Lead to drive test architecture and silicon implementation for next-generation 2.5D / 3D designs. This is a hands-on technical leadership role for an engineer who has spent a career shipping production silicon and is excited to take on chiplet-, interposer-, and HBM-class complexity.

You will work alongside design, verification, packaging, and post-silicon teams to define testability strategy end-to-end — from RTL DFT insertion through pattern