Senior DFT Architect — Next-Gen Silicon Test & Equity

NVIDIA AI; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA is seeking an experienced Design-for-Test Engineer in Santa Clara, CA to own DFT architectures, develop test access mechanisms, and deploy DFX strategies across products. You will collaborate with system and chip teams to optimize test quality and support silicon bring-up and debugging on industry-leading processors.

The role requires strong scripting skills (Perl/Python/Tcl), extensive DFT knowledge, and the ability to mentor junior engineers while navigating cross-functional design

Qualifications

• BSEE (or equivalent experience) with 8+ years, MSEE with 5+ years of experience or PhD with 3+yrs in DFT or related domains
• Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
• Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
• Strong programming and scripting skills in Perl, Python or Tcl desired
• Extraordinary written and oral communication skills with the curiosity to work on rare challenges

Responsibilities

• Own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression
• Help develop and deploy DFT methodologies for our next generation products
• Define, prototype and deploy next generation DFX architectures and methodologies across all products
• Craft key DFX architecture and methodologies to meet system level safety diagnostic test quality and in-field test quality
• Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations
• Deliver efficient workflows and tools to productize features on leading processors for deep learning, gaming, HPC and supercomputing
• Mentor junior engineers on test designs and trade-offs including cost and quality

Skills

Perl

Python

Tcl

DFT

Education

BSEE (or equivalent)

MSEE

PhD

Tools

ATPG tools

Job description

NVIDIA is seeking an experienced Design-for-Test Engineer in Santa Clara, CA to own DFT architectures, develop test access mechanisms, and deploy DFX strategies across products. You will collaborate with system and chip teams to optimize test quality and support silicon bring-up and debugging on industry-leading processors.

The role requires strong scripting skills (Perl/Python/Tcl), extensive DFT knowledge, and the ability to mentor junior engineers while navigating cross-functional design