Lead ASIC DFT Architect - Testability & Post-Silicon Expert

itD Tech; Carlsbad, Allentown (CA, Lehigh County); Hybrid; USD 140,000 - 200,000; Full time

Job summary

itD is seeking a DFT Lead to drive implementation of advanced DFT solutions across the silicon development lifecycle, ensuring highly testable, manufacturable ASIC designs. The candidate will lead cross-functional teams to deliver production-ready silicon.

Requirements include 8–10+ years in ASIC DFT, hands-on experience with JTAG, MBIST, BISR, boundary scan, ATPG, and industry tools like Tessent, Xcelium, Genus, Tempus or PrimeTime.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• 8–10+ years of ASIC DFT engineering experience.
• Hands-on with JTAG, scan architectures, MBIST, BISR, boundary scan, and third-party IP.

Responsibilities

• Lead DFT feature implementation across the ASIC design lifecycle.
• Develop and integrate DFT IP and testability into RTL.
• Perform post-silicon debugging and production qualification to improve yield and manufacturability.
• Collaborate with physical design, validation and hardware teams throughout the lifecycle.
• Design and release ATPG patterns; support manufacturing readiness and ramp.

Skills

DFT engineering

JTAG protocols

MBIST

BISR

Boundary scan

ATPG methods

Post-silicon debugging

Test architecture

Cross-functional leadership

Education

Bachelor's in Electrical/Computer Engineering

Master's degree preferred

Tools

Tessent

Xcelium

Genus

Tempus

PrimeTime

Job description

itD is seeking a DFT Lead to drive implementation of advanced DFT solutions across the silicon development lifecycle, ensuring highly testable, manufacturable ASIC designs. The candidate will lead cross-functional teams to deliver production-ready silicon.

Requirements include 8–10+ years in ASIC DFT, hands-on experience with JTAG, MBIST, BISR, boundary scan, ATPG, and industry tools like Tessent, Xcelium, Genus, Tempus or PrimeTime.