Lead DFT & MBIST Architect for Production Silicon

Fortell Research Inc.; San Francisco (CA); Hybrid; USD 160,000 - 300,000; Full time

Benefits offered by this job

Stock options

Generous benefits package

Job summary

A leading technology firm based in California is seeking an experienced DFT Engineer to lead full-chip test architecture and ensure production-ready silicon with diagnostic capability. The role involves designing comprehensive DFT structures and collaborating with cross-functional teams. Candidates should have a strong background in DFT standards and proficiency in Cadence tools. The target salary range is competitive, reflecting skills and experience, alongside a generous benefits package.

Qualifications

• Strong understanding of DFT, ATPG, JTAG, and MBIST.
• Proven experience in developing DFT specifications for complex designs.
• Expertise in debugging DFT issues and coverage analysis.

Responsibilities

• Develop and implement comprehensive DFT structures tailored to design requirements.
• Design robust DFT infrastructure including scan chains and test mechanisms.
• Generate ATPG test vectors and analyze DFT coverage.

Skills

Understanding of industry standards in DFT

Experience in debugging DFT issues

Scripting skills using TCL

Proficiency in Cadence tools

Tools

Cadence Modus

Cadence Genus

Job description

A leading technology firm based in California is seeking an experienced DFT Engineer to lead full-chip test architecture and ensure production-ready silicon with diagnostic capability. The role involves designing comprehensive DFT structures and collaborating with cross-functional teams. Candidates should have a strong background in DFT standards and proficiency in Cadence tools. The target salary range is competitive, reflecting skills and experience, alongside a generous benefits package.