Lead DFT Architect for Photonic AI ASICs

Socket.dev; Austin (TX); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Health insurance

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Job summary

Neurophos is hiring a DFT Architect to own design-for-test for our electronic ICs. You will set the DFT strategy for the full chip, own coverage assessment and signoff, and collaborate with RTL and physical design teams to build testability in from the start.

This is our first dedicated DFT hire, shaping the testing approach and growing the team. You will define test requirements with the analog team, drive system-level wafer and package test plans, and push for rapid, production-ready test

Qualifications

• 8–15 years in DFT with hands-on ownership of scan, ATPG and MBIST.
• Architect-level experience on a large digital ASIC with full-chip DFT strategy and coverage signoff.
• Experience developing and specifying functional test vectors to augment structural coverage.
• Track record through tapeout on a complex compute ASIC.

Responsibilities

• Own DFT architecture and test control design for ASIC devices using ATPG, scan, MBIST, and JTAG.
• Architect on-die memory test, including controller specification and generation, pattern selection, RAM grouping, and system test timing.
• Collaborate with operations and PE teams to ensure all test modes are implemented, including HAST and qualification functions.
• Architect system-level wafer and package DFT plans for all product development phases.
• Create and deploy integrated DFT development flow with metrics for quick analysis and updates to near 100% test coverage.
• Own coverage assessment and signoff, including strategic decisions on gaps.

Skills

DFT architecture

ATPG

MBIST

Digital ASIC

Test vector development

silicon photonics test

AI tooling in DFT

Tools

Cadence toolchain

Analog test

Photonic DFT exposure

Job description

Neurophos is hiring a DFT Architect to own design-for-test for our electronic ICs. You will set the DFT strategy for the full chip, own coverage assessment and signoff, and collaborate with RTL and physical design teams to build testability in from the start.

This is our first dedicated DFT hire, shaping the testing approach and growing the team. You will define test requirements with the analog team, drive system-level wafer and package test plans, and push for rapid, production-ready test