DFT Lead

Eximietas Design; San Francisco (CA); Hybrid; USD 190,000 - 250,000; Full time

Job summary

Eximietas Design is hiring a seasoned DFT Lead to drive test architecture and silicon implementation for next-generation 2.5D / 3D designs. This is a hands-on technical leadership role for an engineer who has spent a career shipping production silicon and is excited to take on chiplet-, interposer-, and HBM-class complexity.

You will work alongside design, verification, packaging, and post-silicon teams to define testability strategy end-to-end — from RTL DFT insertion through pattern

Qualifications

• 10–15 years of hands-on DFT engineering experience.
• Production silicon tapeout in lead role.
• ATPG expertise with Synopsys TetraMAX, Mentor Tessent, or Cadence Modus.
• Deep knowledge of scan compression, MBIST, LBIST, and BIST.
• Experience with JTAG/Boundary Scan and IEEE 1149.x/1687.
• Experience with 2.5D/3D design and chiplet interconnect test.
• Strong fault models and coverage analysis background.
• Strong debugging and problem-solving in silicon labs.
• Clear communication to align teams and stakeholders.

Responsibilities

• Define and own the DFT architecture for advanced packaging.
• Lead ATPG strategy and implementation using specified tools.
• Architect and integrate scan/MBIST/LBIST/BIST across SoCs.
• Design and validate JTAG/Boundary Scan and IEEE networks.
• Partner with packaging and physical design to meet DFT needs.
• Support post-silicon validation and ATE bring-up.
• Mentor and grow DFT engineering capability.
• Interface with stakeholders to communicate DFT plans and risks.

Skills

DFT engineering

ATPG expertise

Scan compression

MBIST/LBIST/BIST

JTAG/Boundary Scan

2.5D/3D design knowledge

Fault models & coverage

Debug & problem solving

Clear communicator

Tools

Synopsys TetraMAX

Mentor Tessent

Cadence Modus

Job description

Type: Full-time

Location: Bay Area, California/Austin, TX — primarily onsite with hybrid flexibility

Experience: 10–15 years

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About the role

Eximietas Design is hiring a seasoned DFT (Design for Test) Lead to drive test architecture, methodology, and silicon implementation for next-generation 2.5D / 3D designs. This is a hands-on technical leadership role for an engineer who has spent a career shipping production silicon and is excited to take on chiplet-, interposer-, and HBM-class complexity.

You will work alongside design, verification, packaging, and post-silicon teams to define testability strategy end-to-end — from RTL DFT insertion through pattern generation, ATE bring-up, and yield ramp.

What you'll do

• Define and own the DFT architecture for advanced packaging projects (2.5D, 3D, chiplet, interposer, HBM stacks).
• Lead ATPG strategy and implementation using Synopsys TetraMAX, Mentor (Siemens) Tessent, or Cadence Modus — pattern generation, coverage analysis, fault models, X-handling, and compression.
• Architect and integrate scan, MBIST, LBIST, and BIST infrastructure across complex SoCs, ensuring high coverage with low area and timing overhead.
• Design and validate JTAG, Boundary Scan, and IEEE 1149.x / 1687 (IJTAG) networks, including hierarchical access for multi-die systems.
• Partner with packaging and physical design teams to ensure DFT requirements are met for 2.5D / 3D test access, inter-die test, and known-good-die (KGD) flows.
• Support post-silicon validation and ATE bring-up, debug test pattern issues, and drive root-cause analysis on first-silicon escapes.
• Mentor and grow DFT engineering capability within the team — code reviews, methodology documents, and best-practice guidelines.
• Interface with executive stakeholders, customers, and program leads to communicate DFT plans, risks, and trade-offs.

What we're looking for (must-have)

• 10–15 years of hands-on DFT engineering experience, ideally with at least one production silicon tapeout in a lead role.
• Strong ATPG expertise with at least one of: Synopsys TetraMAX, Mentor (Siemens) Tessent, Cadence Modus.
• Deep working knowledge of scan compression, MBIST, LBIST, and BIST architecture and implementation.
• Hands-on experience with JTAG, Boundary Scan, and IEEE 1149.x / 1687 standards in complex SoC environments.
• Demonstrated experience with 2.5D / 3D design — chiplet integration, interposer-based test access, HBM test flows, or equivalent advanced packaging exposure.
• Strong fault models and coverage analysis background — transition, stuck-at, IDDQ, cell-aware.
• Excellent debug and problem-solving instincts — comfortable in silicon labs, ATE floors, and with production yield data.
• Clear communicator — able to align technical teams and present DFT trade-offs to non-DFT stakeholders.

Nice to have

• Post-silicon validation and ATE platform bring-up (Advantest, Teradyne, etc.)
• Low-power DFT methodology
• Hierarchical and divide-and-conquer DFT for multi-die systems
• Experience with formal DFT verification flows
• Familiarity with UCIe and chiplet interconnect test
• Past leadership of small DFT teams (3–8 engineers)

Eximietas Design is a semiconductor and embedded systems design services partner working with leading silicon companies and chip startups. Our engineers contribute to some of the most demanding production silicon programs in the industry. As a DFT Lead, you'll have a direct hand in shipping advanced-node, advanced-packaging products — and the autonomy to set the DFT direction for those programs.

• Full-time, permanent role (this is not a contract)
• Primarily onsite in the Bay Area with hybrid flexibility
• Immediate start preferred — short notice candidates strongly encouraged to apply