Lead DFT Architect for Chiplet & 3DIC Test

Eliyan Corporation; San Francisco (CA); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Onsite M-F

Excellent benefits

Job summary

Eliyan Corporation is seeking a DFT Implementation Lead to drive full DFT architecture for 2.5D/3DIC chiplet products. You will own DFT strategy, select tools, and lead cross-functional teams across digital, analog, and physical design to deliver high-quality test solutions for multi-die silicon.

You will work onsite in a fast-paced startup environment, contributing to innovative DFT methods, KGD strategies, and scalable test infrastructure while mentoring teams and ensuring seamless validation

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• At least 15 years of hardware DFT, testability, and physical design experience.
• Proven expertise in JTAG, scan, BIST, and boundary scan.
• Experience with ATPG and EDA tools (Tessent, TetraMax, Genus, Tempus, DC, PrimeTime).
• Hands-on DFT for 2.5D/3DIC and chiplet-based systems across pre-, mid-, post-bond test.

Responsibilities

• Develop and implement DFT IP and features for ATE and in-system test.
• Collaborate with digital, analog, and physical design teams on flow/methodology.
• Integrate DFT features into RTL design and validate/test.
• Define DFT constraints and sign-off across multi-mode/multi-corner.
• Own architecture, tool/vendor selection for DFT insertion and debugging.
• Create DFT collateral and architecture documents for chiplets and PHYs.
• Define KGD test and screening strategies for chiplets and hard IP.

Skills

DFT architecture

Cross-functional collaboration

Scripting (Tcl/Python/Perl)

Problem solving

Experience in start-up environment

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Tessent

TetraMax

Genus

Tempus

Mentis/DC/PrimeTime

Job description

Eliyan Corporation is seeking a DFT Implementation Lead to drive full DFT architecture for 2.5D/3DIC chiplet products. You will own DFT strategy, select tools, and lead cross-functional teams across digital, analog, and physical design to deliver high-quality test solutions for multi-die silicon.

You will work onsite in a fast-paced startup environment, contributing to innovative DFT methods, KGD strategies, and scalable test infrastructure while mentoring teams and ensuring seamless validation