Design Verification Engineer

Apple Inc.; United States; Presencial; USD 140.000 - 230.000; Jornada completa

Descripción de la vacante

Apple Inc. is seeking an outstanding Design Verification Engineer to help deliver bug-free first silicon for IP designs. You will establish DV methodologies, develop verification environments with stimulus and checkers, and drive test plans through RTL freeze and tape-out.

A strong background in SystemVerilog, UVM, and scalable test-benches is essential. With a BS degree and 10+ years of experience, you will leverage robust scripting skills (Python/Perl/TCL) and experience with PCIe/DDR or

Formación

• BS degree in technical subject area with 10+ years of industry experience.
• Strong knowledge of OOP, SystemVerilog and UVM.
• Experience designing scalable, portable test-benches and verification plans.
• Proficient in Python, Perl, and TCL scripting.

Responsabilidades

• Define and implement DV methodology and verification environments for pre-silicon IP designs.
• Develop test plans, stimulus, checkers, and coverage to achieve bug-free silicon.
• Write, debug, and maintain test-benches across IP, block, and SoC levels.
• Track and report DV progress using metrics such as bugs and coverage; support RTL freeze and tape-out.
• Leverage LLMs to improve verification efficiency and quality.

Conocimientos

OOP

Test bench design

Verification methodologies

Debugging

Automation scripting

Power-aware verification concepts

Educación

BS degree in technical subject area

Herramientas

SystemVerilog

UVM

Python

Perl

TCL

PCIe

USB

DDR

LLMs

emulation

Descripción del empleo

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers daily.

This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.

Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.

Minimum Qualifications

BS degree in technical subject area and a minimum 10 years relevant industry experience.

Preferred Qualifications

Deep knowledge of OOP, SystemVerilog and UVM

Deep knowledge in developing scalable and portable test-benches

Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations

Working experience using LLMs for efficiency and quality

Experience with power-aware (UPF) or similar verification methodology

Excellent knowledge of one of the scripting languages such as Python, Perl, TCL

Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required

Knowledge of formal verification methodology is a plus but not required

Knowledge of emulation for verification technologies is a plus but not required